1. Field of the Disclosure
The present invention is directed to terminating interconnect structures and to coupling between chips and substrates.
2. Description of the Related Art
Driven by an ever greater demand for miniaturization of ever more complex electronic components, consumer electronics such as computing and telecommunication devices are becoming more integrated. This has created a need for support structures such as IC substrates and IC interposers that have a high density of multiple conductive layers and vias that are electrically insulated from each other by a dielectric material.
The general requirement for such support structures is reliability and appropriate electrical performance, thinness, stiffness, planarity, good heat dissipation and a competitive unit price.
Of the various approaches for achieving these requirements, one widely implemented manufacturing technique that creates interconnecting vias between layers uses lasers to drill holes through the subsequently laid down dielectric substrate through to the latest metal layer for subsequent filling with a metal, usually copper, that is deposited therein by a plating technique. This approach to creating vias is sometimes referred to as ‘drill & fill’, and the vias created thereby may be referred to as ‘drilled & filled vias’.
There are a number of disadvantages with the drilled & filled via approach. Since each via is required to be separately drilled, the throughput rate is limited, and the costs of fabricating sophisticated, multi-via IC substrates and interposers becomes prohibitive. In large arrays it is difficult to produce a high density of high quality vias having different sizes and shapes in close proximity to each other by the drill & fill methodology. Furthermore, laser drilled vias have rough sides walls and taper inwards through the thickness of the dielectric material. This tapering reduces the effective diameter of the via. It may also adversely affect the electrical contact to the previous conductive metal layer especially at ultra small via diameters, thereby causing reliability issues. Additionally, the side walls are particularly rough where the dielectric being drilled is a composite material comprising glass or ceramic fibers in a polymer matrix, and this roughness may result in stray inductances.
The filling process of the drilled via holes is usually achieved by copper electroplating. Electroplating into a drilled hole may result in dimpling, where a small crater appears at the end of the via. Alternatively, overfill may result, where a via channel is filled with more copper than it can hold, and a domed upper surface that protrudes over the surrounding material is created. Both dimpling and overfill tend to create difficulties when subsequently stacking vias one on end of the other, as required when fabricating high-density substrates and interposers. Furthermore, it will be appreciated that large via channels are difficult to fill uniformly, especially when they are in proximity to smaller vias within the same interconnecting layer of the interposer or IC substrate design.
Although the range of acceptable sizes and reliability is improving over time, the disadvantages described hereinabove are intrinsic to the drill & fill technology and are expected to limit the range of possible via sizes. It will further be noted that laser drilling is best for creating round via channels. Although slot shaped via channels may theoretically be fabricated by laser milling, in practice, the range of geometries that may be fabricated is somewhat limited and vias in a given support structure are typically cylindrical and substantially identical.
Fabrication of vias by drill & fill is expensive and it is difficult to evenly and consistently fill the via channels created thereby with copper using the relatively, cost-effective electroplating process.
Laser drilled vias in composite dielectric materials are practically limited to a minimum diameter of 60×10−6 m, and even so suffer from significant tapering shape as well as rough side walls due to the nature of the composite material drilled, in consequence of the ablation process involved.
In addition to the other limitations of laser drilling as described hereinabove, there is a further limitation of the drill & fill technology in that it is difficult to create different diameter vias in the same layer, since when drill different sized via channels are drilled and then filled with metal to fabricate different sized vias, the via channels fill up at different rates. Consequently, the typical problems of dimpling or overfill that characterize drill & fill technology are exasperated, since it is impossible to simultaneously optimize deposition techniques for different sized vias.
An alternative solution that overcomes many of the disadvantages of the drill & fill approach, is to fabricate vias by depositing copper or other metal into a pattern created in a photo-resist, using a technology otherwise known as ‘pattern plating’.
In pattern plating, a seed layer is first deposited. Then a layer of photo-resist is deposited thereover and subsequently exposed to create a pattern, and selectively removed to make trenches that expose the seed layer. Via posts are created by depositing Copper into the photo-resist trenches. The remaining photo-resist is then removed, the seed layer is etched away, and a dielectric material that is typically a polymer impregnated glass fiber mat, is laminated thereover and therearound to encase the via posts. Various techniques and processes can then be used to planarize the dielectric material, removing part of it to expose the ends of the via posts to allow conductive connection to ground thereby, for building up the next metal layer thereupon. Subsequent layers of metal conductors and via posts may be deposited there onto by repeating the process to build up a desired multilayer structure.
In an alternative but closely linked technology, known hereinafter as ‘panel plating’, a continuous layer of metal or alloy is deposited onto a substrate. A layer of photo-resist is deposited on end of the substrate, and a pattern is developed therein. The pattern of developed photo-resist is stripped away, selectively exposing the metal thereunder, which may then be etched away. The undeveloped photo-resist protects the underlying metal from being etched away, and leaves a pattern of upstanding features and vias.
After stripping away the undeveloped photo-resist, a dielectric material, such as a polymer impregnated glass fiber mat, may be laminated around and over the upstanding copper features and/or via posts. After planarizing, subsequent layers of metal conductors and via posts may be deposited there onto by repeating the process to build up a desired multilayer structure.
The via layers created by pattern plating or panel plating methodologies described above are typically known as ‘via posts’ and feature layers from copper.
It will be appreciated that the general thrust of the microelectronic evolution is directed towards fabricating ever smaller, thinner, lighter and more powerful products having high reliability. The use of thick, cored interconnects, prevents ultra-thin products being attainable. To create ever higher densities of structures in the interconnect IC substrate or ‘interposer’, ever more layers of ever smaller connections are required. Indeed, sometimes it is desirable to stack components on end of each other.
If plated, laminated structures are deposited on a copper or other appropriate sacrificial substrate, the substrate may be etched away leaving free standing, coreless laminar structures. Further layers may be deposited on the side previously adhered to the sacrificial substrate, thereby enabling a two sided build up, which minimizes warping and aids the attaining of planarity.
One flexible technology for fabricating high density interconnects is to build up pattern or panel plated multilayer structures consisting of metal vias or via post features having various geometrical shapes and forms in a dielectric matrix. The metal may be copper and the dielectric may be a fiber reinforced polymer, typically a polymer with a high glass transition temperature (Tg) is used, such as polyimide, for example. These interconnects may be cored or coreless, and may include cavities for stacking components. They may have odd or even numbers of layers and the via may have non circular shapes. Enabling technology is described in previous patents issued to Amitec-Advanced Multilayer Interconnect Technologies Ltd.
For example, U.S. Pat. No. 7,682,972 to Hurwitz et al. titled “Advanced multilayer coreless support structures and method for their fabrication” describes a method of fabricating a free standing membrane including a via array in a dielectric, for use as a precursor in the construction of superior electronic support structures, includes the steps of fabricating a membrane of conductive vias in a dielectric surround on a sacrificial carrier, and detaching the membrane from the sacrificial carrier to form a free standing laminated array. An electronic substrate based on such a free standing membrane may be formed by thinning and planarizing the laminated array, followed by terminating the vias. This publication is incorporated herein by reference in its entirety.
U.S. Pat. No. 7,669,320 to Hurwitz et al. titled “Coreless cavity substrates for chip packaging and their fabrication” describes a method for fabricating an IC support for supporting a first IC die connected in series with a second IC die; the IC support comprising a stack of alternating layers of copper features and vias in insulating surround, the first IC die being bondable onto the IC support, and the second IC die being bondable within a cavity inside the IC support, wherein the cavity is formed by etching away a copper base and selectively etching away built up copper. This publication is incorporated herein by reference in its entirety.
U.S. Pat. No. 7,635,641 to Hurwitz et al. titled “integrated circuit support structures and their fabrication” describes a method of fabricating an electronic substrate comprising the steps of; (A) selecting a first base layer; (B) depositing a first etchant resistant barrier layer onto the first base layer; (C) building up a first half stack of alternating conductive layers and insulating layers, the conductive layers being interconnected by vias through the insulating layers; (D) applying a second base layer onto the first half stack; (E) applying a protective coating of photo-resist to the second base layer; (F) etching away the first base layer; (G) removing the protective coating of photo-resist; (H) removing the first etchant resistant barrier layer; (I) building up a second half stack of alternating conductive layers and insulating layers, the conductive layers being interconnected by vias through the insulating layers, wherein the second half stack has a substantially symmetrical lay up to the first half stack; (J) applying an insulating layer onto the second half stack of alternating conductive layers and insulating layers, (K) removing the second base layer, and (L) terminating the substrate by exposing ends of vias on outer surfaces of the stack and applying terminations thereto. This publication is incorporated herein by reference in its entirety.
The via post technology described in U.S. Pat. No. 7,682,972, U.S. Pat. No. 7,669,320 and U.S. Pat. No. 7,635,641 lends itself to mass production, with very large numbers of vias being simultaneously electroplated. As mentioned above, current drill & fill vias have an effective minimal diameter of about 60 microns. In contradistinction, via post technology using photo resist and electroplating, enables higher densities of vias to be obtained. Via diameters of as little as 30 micron diameter are possible and various via geometries and shapes could be cofabricated within the same layer.
Over time, it is anticipated that both drill & fill technologies and via post deposition will enable fabrication of substrates with further miniaturization and higher densities of vias and features. Nevertheless, it would appear likely that developments in via post technology will maintain a competitive edge.
Substrates enable chips to interface with other components. Chips have to be bonded to substrates in a manner that provides reliable electronic connections to enable electronic communication between chips and substrates.
Among the high density leading technology to interconnect the Substrate to Chips is the well established “Flip Chip technology” in which Solder bumps, Lead free solder bumps, or copper bumps having solder or lead free solder on their tips, are grown on the Chip terminating pads and the Chip is then flipped over to interconnect its bumps on the top surface pads of the Substrate. As Chip bumps and pitches are becoming denser, advanced Substrates are usually equipped with bumps of their own to assist with the interconnection to the chip bumps. Such bumps on the substrate pads are also known as “SoP” (Solder on Pad”) bumps—and usually consist of solder or lead free solder. They are generally applied to the substrate terminating pads by stencil printing followed by reflow, or by electro-less or electroplating processes followed by reflow.
When the Chip bumps come in contact with the SoP bumps through reflow, the solder material of the SoP bumps helps to generate a reliable mechanical and electronic contact with the Chip bump. Without the SoP, the solder material of the chip bumps may not be sufficient or may not be able to completely flow and wet the entire surface of the substrate's terminating pad thereby creating a reliability hazard or even a disconnect between the chip and the substrate. This is an especially a valid concern since most of the substrates have a solder mask external protective layer that by nature extends above the terminating substrate pads thereby making these pads difficult to access without the SoP bumps.
It is known to those familiar in the art that the size and pitch of Chip bumps must be aligned as much possible to those of the SoP bumps. With ongoing developments in chip technology, chips become ever denser, and connection bumps will become ever denser as ever higher concentrations of contacts are required. Consequently, the application of SoP bumps on the substrate becomes ever more challenging. The application of SoP is by nature, a lower yield process than earlier substrate manufacturing steps, and it is one of the final processing steps in the substrate fabrication, thereby increasing scarp, rework, test and cost rates. Additionally, the more fine the pitch of subsequent generations of SoP bumps, the greater the likelihood of failure by shorting between adjacent bumps after reflow and during chip assembly will be, thereby further reducing yields and increasing the total package cost.
As post sizes shrink, it becomes ever more difficult to keep individual wires electronically isolated from each other to prevent shorting. Soldering is also tricky, in that too little solder may result in some connections being broken. However, too much solder risks shorting between nearby connections.
Embodiments of the present invention address these issues.